# Project 907 — Access to State-of-the-Art (SOTA) Microelectronics - Development

**Program element:** 0604294D8Z — Trusted and Assured Microelectronics  
**Project:** 907  
**Component:** Defense-Wide  
**Appropriation:** 0400 — RDT&E, Defense-Wide  
**Budget Activity:** 4 — Advanced Component Development & Prototypes  
**Vintage:** President's Budget PB2027  
**Canonical URL:** https://hitchintel.com/programs/0604294D8Z/907  
**Parent:** https://hitchintel.com/programs/0604294D8Z

## Summary

Project 907 — Access to State-of-the-Art (SOTA) Microelectronics - Development requests $14.9M in FY2027, 9.5% of the $156.7M requested for program element 0604294D8Z, down 88% on FY2026. 2 R-2A activities decompose the request.

## Funding profile

| Fiscal Year | Estimate Type | Amount ($M) |
|---|---|---|
| FY2025 | Actual | 311.8 |
| FY2026 | Enacted | 125.0 |
| FY2027 | Request | 14.9 |
| FY2028 | Outyear | 15.5 |
| FY2029 | Outyear | 15.7 |
| FY2030 | Outyear | 16.0 |
| FY2031 | Outyear | 16.0 |

> Estimate types are not summed. This project is one leaf of PE 0604294D8Z; the PE total is the sum of its projects, never added to them.

## What project 907 buys

This project establishes strategic partnerships with commercial SOTA domestic foundries to develop a data-driven, risk- based approaches to supply chain protection and develops the assured access, secure design, and manufacturing capability of advanced microelectronics technology and electronic components. This project funds microelectronics software assurance (SwA) support to DoW programs and supports the activities of the Joint Federated Assurance Center (JFAC), codified in the National Defense Authorization Act (NDAA) for Fiscal Year 2025, Sec 922, to support the assurance needs of the DoW by ensuring, pursuant to policies related to hardware and software assurance and supply chain risk management, that the software and hardware developed, acquired, maintained, and used by the Department are free from intentional and unintentional vulnerability during the life-cycle of development and deployment of assured, trustworthy defense systems. Projects are transitioning technologies into DoW systems and platforms, ensuring access to multiple onshore commercial microelectronics facilities, establishing secure design capabilities, implementing an evidence-based approach to supply chain protection, and developing technologies for situational awareness of the global microelectronics supply chain. This project builds the foundation for updating and strengthening DoW assurance methods and standards with industry to develop data driven evidence-based practices.

**R-3 lines of work:** Product Development.

## Activities (R-2A) — 2

| Activity | FY2025 | FY2026 | FY2027 | Move | Page |
|---|---|---|---|---|---|
| Joint Federated Assurance Center (JFAC) | — | 9.1 | 9.5 | +5% | — |
| Access to State-of-the-Art (SOTA) Microelectronics - Development | 311.8 | 115.9 | 5.4 | −95% | — |

> Activities carry the prior, current and budget year only — no five-year plan. In the request year they partition this project exactly; in earlier years they can under-cover it.

### Joint Federated Assurance Center (JFAC)

**FY2027 planned work.** Evaluate state-of-the-art software assurance (SwA) tools applicable to DoW needs for enhanced microelectronics software assurance; conduct an assessment of formal methods as applied to specific DoW SwA needs; advance technology for detection of malicious and subverted code in DoW embedded systems and evaluate against ground truth; map vulnerabilities and threats to SwA tool capabilities and provide assessments of SwA tool effectiveness; develop both embedded software and software tools to address supply chain vulnerabilities, bill of materials (BoM) validation, and integrity of intellectual property (IP) blocks.

**FY2026 to FY2027 change.** The increase of $0.441 million from FY 2026 to FY 2027 is due to priority realignment for DoW critical technologies

**FY2026 plans — current year.** Select, procure, and adapt quantities of state-of-the-art software assurance (SwA) tools; innovate and advance technology for detection of malicious and subverted code in DoW embedded systems; determine and mitigate exploitable vulnerabilities; map vulnerabilities and threats to SwA tool capabilities and provide assessments of SwA tool effectiveness; develop both embedded software and software tools to address supply chain vulnerabilities, bill of materials (BoM) validation, and integrity of intellectual property (IP) blocks.

### Access to State-of-the-Art (SOTA) Microelectronics - Development

**FY2027 planned work.** Focus the scope of SOTA Access efforts to deliver end-to-end design, tape out, test and evaluation for specific chips in concert with transition partners. These efforts include application specific integrated circuits (ASICs) for communications and imaging applications.

**FY2026 to FY2027 change.** The decrease of $110.522 million between FY 2026 and FY 2027 is due to priority realignment for DoW critical technologies.

**FY2026 plans — current year.** Foundry Access and RAMP-C: Completion of the dedicated RAMP-C project to leverage the leading edge (<7 nanometer), commercially-viable, U.S.-located domestic wafer foundry ecosystem for design and manufacturing of evidence-based assured, dual-use commercial and DoW custom integrated circuits. Evolution of RAMP-C to transition-focused development of microelectronics devices with enhanced mission capability by leveraging <7 nanometer microelectronics manufacturing. This project will: • Continue to enhance access to state-of-the-art (SOTA) fabrication ecosystem. • Maintain program of record access to assured fabrication flow and fund multi-project wafer production runs at multiple SOTA domestic sources. • Continue growth in commercial and government use of the most advanced domestic foundries by key U.S. fabless companies. • Leverage a digital engineering/design ecosystem including access to 3rd party design modules. • Promote modeling and simulation to anticipate performance benefits to be derived from design and fabrication of DoW microelectronics in advanced (<7 nm) technologies. • Utilize commercially-supported and enduring U.S. logic foundry capability. • Leverage the expertise of commercial industry to develop and demonstrate novel capabilities for design of State-of-the Art (SOTA) microelectronics with assurance. Domain Specific Design and Transition: • Leverage EDA tools for emulation based evidence-based assurance design flows. • Construct domain-specific architectures that leverage commercial intellectual property (IP), EDA, and processes enabling accelerated prototype demonstration and transition. • Continue to expand and accelerate development and evaluation, and initiate insertion of IP, for application-specific integrated circuit (ASIC) and Chiplet security including authentication, Firmware Attestation and Decryption and system-on-chip (SOC) Interface encryption. • Continue to develop and evaluate, and initiate insertion of, tools and techniques to protect silicon IP during packaging and test phase, including multi-chip package (MCP). • Continue leverage of trusted commercial off-the-shelf (COTS) parts in for DoW applications. Artificial Intelligence Hardware at the Edge: • Conduct ongoing evaluation of the NorthPole AI inference processor against emerging commercial technologies for DoW applications. • Identify demonstration opportunities to support transition of Northpole technology for operational use. • Investigate the potential of Neuromorphic AI processors that are robust radiation tolerant, low power and low latency for real-time onboard AI and autonomy capabilities for future DoW and intelligence community systems across all operational domains (space, land, air, sea).

**FY2025 accomplishments.** Foundry Access: • Continue to enhance access to state-of-the-art (SOTA) fabrication ecosystem. • Maintain program of record access to assured fabrication flow and fund multi-project wafer production runs at multiple SOTA domestic sources. RAMP-C: A leading edge (<7 nanometer), commercially-viable, U.S.-located domestic wafer foundry ecosystem access is established. The ecosystem will have capability on the order of > 26,000 wafer starts per month for design and manufacturing of evidence-based assured, dual-use commercial and DoD custom integrated circuits. This project will enable the following: • Access, meaning the ability for DoD programs and the defense industrial base to purchase parts and devices with the necessary assurance, to a SOTA U.S. wafer foundry, to commercial and critical evidence-based assured dual-use COTS integrated circuits, and to capabilities necessary to develop evidence-based assured custom DoD integrated circuits. • The jump-start in commercial use of the domestic foundry by key U.S. fabless companies. • Establishment of a viable design ecosystem including access to 3rd party design modules. • The reduction in the cost differential of building a U.S.-located wafer foundry verses off-shore. • The enablement of commercially-supported and enduring U.S. logic foundry capability. • Leverage the expertise of commercial industry to develop and demonstrate novel capabilities for design of State-of-the Art (SOTA) with assurance. Cloud/Electronic Design Automation (EDA): • Continue activities for prototype demonstration of an emulation based evidence-based assurance design flows • Continue efforts to raise the technology readiness level (TRL) of pilot emulation efforts to production readiness by standardizing the cloud-based emulation workflows, enhancing the robustness of the flows, and bringing them up to IL-4 Design Acceleration and Transition: • Continue activities with Design Acceleration Centers to leverage commercial intellectual property (IP), EDA, and processes enabling prototype transition acceleration • Continue to expand and accelerate development and evaluation and initiate insertion of IP for application-specific integrated circuit (ASIC) and Chiplet security including authentication, Firmware Attestation and Decryption and system-on-chip (SOC) Interface encryption. • Continue to develop and evaluate, and initiate insertion of, tools and techniques for Protect of silicon IP during manufacturing and test phase, including multi-chip package (MCP). • Continue development of using commercial off-the-shelf (COTS) parts in more critical DoD applications utilizing the inherent personalization features

## What is NOT on this page

Congressional marks, the R-2 mission description and acquisition strategy, the industry vs government split of the whole request, and related program elements are recorded at **program-element** grain — an NDAA mark lands on a PE, never on a project. They are at https://hitchintel.com/programs/0604294D8Z.

## Source & machine access

- **Source:** FY2027 Office of the Secretary of Defense RDT&E Budget Justification, Exhibits R-2/R-2A/R-3, PE 0604294D8Z project 907 (PB PB2027).
- **MCP:** `mcp.hitchintel.com` — `budget_get_program_element(pe="0604294D8Z")`.

*HitchAI is an independent intelligence service, not affiliated with the U.S. Department of Defense. Budget figures are requests/estimates, not obligations.*