What the FY2027 request buys
Verbatim from the R-2A exhibit for project 912 of PE 0604294D8Z. This is the budget justification's own description of work that has not happened yet — the one thing no other level of the budget carries.
Conduct vulnerability analyses of intellectual property, conduct hardware assessments, integrated circuit verification and validation analyses. Conduct microelectronics situational awareness activities. Develop toolkits and establish transitions for developed toolkits for supply chain vulnerability awareness and bitstream analysis.
The decrease of $113.897 million between FY 2026 and FY 2027 is due to priority realignment for DoW critical technologies.
FY2025–FY2026: what came before
Prior-year accomplishments and current-year plans from the same exhibit. Context for the FY2027 plan, not a series — an activity partitions its project exactly in the request year, but can under-cover it in earlier years.
• Develop FPGA- hardware assurance guidance and best practices to inform risk decisions. • Develop tools, technologies, and techniques to mitigate vulnerabilities in. • Provide FPGA supply chain lifecycle assurance through the development of best practices. • Provide direct technical and analytical support to DoW programs, including risk analysis, validation & verification analysis, and guidance on possible mitigations. • Develop assurance tools, techniques, technology and mitigations to fill assurance gaps within design, physical verification and validation (V&V) and functional testing stages of microelectronic components. • Conduct V&V on FPGA families inform vulnerability mitigations. • Provide technical and analytical support to Military Global Positioning System (GPS) User Equipment (MGUE) program • Provide engineering, technology analysis, and foreign language expertise to the counterintelligence community to support collection, analysis, investigations, and operations related to the DoW and US Government supply chains and foreign intelligence entity (FIE) threats to semiconductor-related equities. • Develop the counterintelligence portal for semiconductor analysis and mitigations to share raw and finished intelligence analysis, intelligence collection, and threat data relating to the semiconductor industry within the law enforcement, counterintelligence, and intelligence communities, as well as key government stakeholders. • Conduct semiconductor familiarization training program for intelligence and counterintelligence personnel. • Conduct supply chain risk-analysis and engagements with the U.S. Semiconductor industry to mitigate supply chain threats • Mature and adopt an evidence-based assurance approach • Support workforce development efforts to build a clearable, knowledgeable workforce to support and execute DoW program workforce modernization needs in microelectronics.
• Continue development of DoD program relevant application prototypes. • Expand number of Joint Federated Assurance Center (JFAC) hardware assurance (HwA) labs that have capabilities which complement existing analytical services. • Conduct proactive Validations & Verification (V&V) on FPGA families • Provide technical and analytical support to Military Global Positioning System (GPS) User Equipment (MGUE) program. Level of support dependent on MGUE requirements. • Stimulate rapid maturation and transition of emerging technologies and co-development with industry for assurance and security. • Continue development of industry outreach strategy to address critical technologies identified by DoD assurance and intelligence analysis. Sharing developed technical threat information with industry partners. • Continue to provide engineering and foreign language expertise to the counterintelligence community to support collection, analysis, investigations, and operations related to the DoD and US Government supply chains and foreign intelligence entity (FIE) threats to semiconductor-related equities. • Continue development of the counterintelligence portal for semiconductor analysis and mitigations (CSPAM) tool to share raw and finished intelligence analysis, intelligence collection, and threat data relating to the semiconductor industry within the law enforcement, counterintelligence, and intelligence communities, as well as key government stakeholders. • Continue the semiconductor familiarization training program for intelligence and counterintelligence personnel and integrate into their established research, development, and acquisition (RDA) training plans. • Continue to perform foreign technology analysis of emerging technologies for the counterintelligence and intelligence communities, to determine semiconductor industry sub-sectors, companies, or technologies that might be the targets of FIE activities, and which foreign companies might be the beneficiaries of foreign targeting. • Expand hardware assurance (HwA) laboratory tools and capabilities to keep pace with emerging commercial developments • Continue conducting supply chain risk-analysis and engagements with the U.S. Semiconductor industry to mitigate supply chain threats • Enable and accelerate maturation and adoption of an evidence-based assurance approach • Mature a regulatory and policy framework to enable long-term access to assured legacy, State-of-the-Practice (SOTP), and SOTA microelectronics. This includes tasks to: Extend access, Evaluate, mature, and improve assurance practices. • Ensure evidence-based assurance approach is aligned with DoD’s comprehensive systems security engineering (SSE) framework. This includes: Trusted Systems and Networks (TSN) Analysis and Component level – FY 2020 NDAA Section 224 response for custom and commercial microelectronics. • Use pilot projects to mature threat driven risk-based decision making models. • Leverage existing efforts, including DoD policy, guidance, threat identification efforts, analysis and response, mitigations, technical efforts, Commercial standards and best practices, and Proactive Technology Analysis. • Support breadth of DoD microelectronics, including Custom – Custom Integrated Circuit (CIC), Field Programmable Gate Array (FPGA), and Commercial – Commercial Off The Shelf (COTS) and modified commercial components. • Cultivate a replicable and scalable Public-Private-Academic Partnership (PPAP) model to attract Science, Technology, Engineering, and Mathematics (STEM) students into trusted and assured microelectronics (T&AM) fields of study Use outreach and curriculum guidance programs for K-12 education, STEM instruction at bachelor’s degree and advanced degree levels, and continuing workforce training efforts to: • Develop a clearable, knowledgeable workforce to support and execute DoD program workforce modernization needs in microelectronics, and • Obtain and maintain an agile and adaptive workforce that meets current, as well as future, DoD needs
Three years, and no five-year plan
An R-2A activity publishes the prior year, the current year and the budget year. The FYDP outyears exist at project and program-element level and are deliberately absent here rather than inferred. Estimate types are colored and never summed into one figure.
| Fiscal Year | Estimate Type | Amount ($M) |
|---|---|---|
| FY2025 | Actual | 140.0 |
| FY2026 | Enacted | 139.5 |
| FY2027 | Request | 25.6 |
This activity is 100% of project 912's FY2027 request and 16% of PE 0604294D8Z's. In the request year the activities under a project sum to it exactly; in the current year they under-cover it in about 9% of cases, so an activity's delta can legitimately exceed its parent's and the two must not be compared row to row.
1 activity in project 912
Every R-2A line of this project, largest FY2027 request first. Linked where the activity has enough of its own narrative to carry a page; the rest are shown in full on the project page.