What the FY2027 request buys
Verbatim from the R-2A exhibit for project 903 of PE 0605294D8Z. This is the budget justification's own description of work that has not happened yet — the one thing no other level of the budget carries.
• Adaptive Compute Acceleration Platform Chiplet (“ACAP”) will complete productization in 1Q FY 2027. • Performance Optimization with Wideband Enhanced Radio-Frequency Unified Package (“POWER-UP”) Multi-Chip Package (MCP) integrating gallium nitride (GaN) high-power amplifiers (HPA), GaN low-noise amplifiers (LNA), and a silicon germanium (SiGe) radio-frequency integrated circuit (RFIC) within a single package fabricated in 150 nm GaN process for GaN MMICs. “BLUE SHELL” to extend the frequency of the POWER-UP MCP, leveraging 90 nm GaN process to increase the maximum MMIC operating frequency, including design, fabrication, and assembly of test boards for functional verification following package assembly. • Prototype Open Architecture Transition Acceleration Chiplet (PORTAL) disaggregation of programmable logic (e.g., FPGA) and Digital Signal Processing (DSP) functionality to optimize FPGA and DSP power, performance, and area requirements on a device- and application-specific basis. FY 2027 plans include advanced packaging, reliability testing, and integration of PORTAL prototypes into existing hardware as a demonstration of PORTAL’s interoperability aimed at modernization programs for the F-15, F-22, and F-35 countermeasures platforms. • Multi-Channel Anti-Jam (MCAJ) Chiplet (MACH-SP): Functional block disaggregation to optimize a GPS MCAJ chiplet based on MGUE Increment 2 ASIC; anti-jam test module verification and anti-jam testing. • “Bantam Bay” Multi-Chip Package (MCP) to reduce the size of the SHIP-RF MCP-1 chip by ~50% with the goal of a 32 mm × 22 mm package size. FY 2027 plans focus on fabrication, packaging, and testing the MCPs. • Ultra-Wideband Quad-Transceiver Chiplet integrating UCIe with the proven architecture and data converter cores of proprietary chiplet to enable full Nyquist signal processing. A demonstrator MCP will be developed with two Ultra-Wideband Quad-Transceiver chiplets integrated in a back-to-back configuration on a silicon interposer to facilitate verification and validation (V&V). Parallel development includes the control algorithms, firmware, and documentation, as well as finalization of the test board design. • Root-of-Security (RoS) Chiplet: Implement Root-of-Trust (CMRT) intellectual property (IP), integrated into a multi-chip package (MCP) with an existing root-of-performance (RoP) field-programmable gate array (FPGA) chiplet. FY 2027 activities include RoS chiplet fabrication in GlobalFoundries 12LP, packaging, and T&E aimed at demonstrating a 50% bill of materials reduction at the circuit card assembly (CCA) level. • Multi-Chip Package (MCP) integrating a Universal Chiplet Interconnect Express (UCIe)-enabled data converter and FPGA chiplets onto a silicon interposer fabricated using 3-Dimensional Universal Package (3DUP) technology for denser integration leading to more power efficient performance as compared to CCA implementations. In mid-FY 2027, interposer fabrication begins, with test board layout.
The decrease of $1.955 million between FY 2026 and FY 2027 is due to priority realignment for DoW critical technologies.
FY2025–FY2026: what came before
Prior-year accomplishments and current-year plans from the same exhibit. Context for the FY2027 plan, not a series — an activity partitions its project exactly in the request year, but can under-cover it in earlier years.
STEAM PIPE is testing advanced MCP technologies in DoW relevant environments and enabling access to advanced packaging processes with capabilities to support ITAR requirements. The Government Lab Advanced Microelectronics – Evaluation & Reporting (GLAM-ER) project is providing DoW labs access to advanced MCP prototype development kits to upskill the government workforce and to assess the prototype capabilities for meeting future DoW requirements. Conduct sub-system and system demonstrations leveraging heterogeneous integrated packaging for DoW transition targets. • Develop advanced packaging prototypes for DoW transition in collaboration with program offices and the (DIB). • Evaluate prototype hardware development kits for meeting DoW future needs. • Develop, test, evaluate, and demonstrate a range of chiplets and multi-chip packages to address DoW needs based on requirements of identified transition partners. These chiplets include capabilities for advanced compute acceleration, high performance RF communications signal amplification and transceivers, digital logic and digital signal processing, anti-jam characteristics, physical miniaturization, root-of-trust and root-of-security, and high-speed data conversion.
• Continue sub-system/system demonstrations leveraging heterogeneous integrated packaging targeting DoD transitions • Continue advanced packaging prototypes targeting DoD transitions • Continue advanced packaging reliability and qualification risk reduction projects • Demonstrate prototype hardware and additional program-driven designs of increasing complexity and capability/performance. • Accelerate and expand the development of multi-chip packaging (MCP) prototype demonstrators in collaboration with DoD Programs and the defense industry for process intensive applications and RF such as AESA Radar, cognitive EW and autonomy, while enhancing security for protecting IP and CPI. • Expand and accelerate demonstration of prototype hardware and additional program-driven designs of increasing complexity and capability/performance: • Layered approach for IP & CPI protection • Enhanced resistance to security and cyber threats • Customized personalization per Program or multi-chip package (MCP) • Risk reduction by much greater visibility into the supply chain and assembly process, including quantifiable data for material tracking, meteorology and process control • Continue to demonstrate enhanced secure design and secure packaging with new tools and techniques.
Three years, and no five-year plan
An R-2A activity publishes the prior year, the current year and the budget year. The FYDP outyears exist at project and program-element level and are deliberately absent here rather than inferred. Estimate types are colored and never summed into one figure.
| Fiscal Year | Estimate Type | Amount ($M) |
|---|---|---|
| FY2025 | Actual | 46.1 |
| FY2026 | Enacted | 27.7 |
| FY2027 | Request | 25.8 |
This activity is 100% of project 903's FY2027 request and 50% of PE 0605294D8Z's. In the request year the activities under a project sum to it exactly; in the current year they under-cover it in about 9% of cases, so an activity's delta can legitimately exceed its parent's and the two must not be compared row to row.
1 activity in project 903
Every R-2A line of this project, largest FY2027 request first. Linked where the activity has enough of its own narrative to carry a page; the rest are shown in full on the project page.